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cy2037 high accuracy eprom programmable pll die for crystal oscillators cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07354 rev. *k revised november 13, 2013 high accuracy eprom programmable pll die for crystal oscillators features erasable programmable read only memory (eprom) - programmable die for in-package programming of crystal oscillators high resolution phase locked loop (pll) with 12-bit multiplier and 10-bit divider eprom programmable capacitor tuning array with optional shadow register twice programmable die simple 2-wire programming interface on-chip oscillator runs from 10 mhz to 30 mhz fundamental tuned crystal eprom-selectable transistor transistor logic (ttl) or complementary metal oxide semi conductor (cmos) duty cycle levels operating frequency: ? 1 mhz to 133 mhz at 5 v ? 1 mhz to 100 mhz at 3.3 v ? 1 mhz to 66.6 mhz at 2.7 v eight selectable post divide options, using pll or reference oscillator output programmable asynchronous or synchronous oe and power-down (pd#) modes(cy2037 and cy2037-2) frequency select (cy2037-3) low jitter outputs typically: ? < 100 ps (pk-pk) at 5 v and f > 33 mhz ? < 125 ps (pk-pk) at 3.3 v and f > 33 mhz 3.3 v or 5 v operation small die controlled rise and fall times and output slew rate functional description cy2037 is an eprom-programmable, high accuracy, pll-based die designed for the crystal oscillator market. the die attaches directly to a low cost 10 to 30 mhz crystal and can be packaged into a 4-pin through-hole or surface mount packages. the oscillator devices may be st ocked as blank parts and custom frequencies programmed in-package at the last stage before shipping. this enables fast-t urn manufacture of custom and standard crystal oscillators without the need for dedicated, expensive crystals. cy2037 contains an on-chip oscillator and a unique oscillator tuning circuit for fine-tuning of the output frequency. the crystal c load may be selectively adjusted by programming a set of seven eprom bits. this feature is used to compensate for crystal variations or to obtain a more accurate synthesized frequency. cy2037 uses eprom programming with a simple 2-wire, 4-pin interface that includes v ss and v dd . clock outputs may be generated up to 133 mhz at 5 v or up to 100 mhz at 3.3 v. the entire configuration can be reprogrammed once, which allows the programmed inventory to be altered or reused. cy2037 pll die is designed for very high resolution. it has a 12-bit feedback counter multiplier and a 10-bit reference counter divider. this enables the synthesis of highly accurate and stable output clock frequencies with zero or low ppm error. the clock is further modified by eight output divider options of 1, 2, 4, 8, 16, 32, 64, and 128. the divider input can be selected as the pll or crystal oscillator output, providing a total of 16 separate output options. for further flexibility, the ouput is selectable between ttl and cmos duty cycle levels. cy2037 also contain flexible power management controls. these parts include both power down (pd#) and output enable (oe) features with in tegrated pull-up resistors. the pd# and oe modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. when pd# or oe modes are en abled, clkout is tri-stated and pulled low by a weak pull-down. in pd# mode, all active circuitry on chip get shutdown, where in oe mode pll and oscillator remain operating. controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable cy2037 to have low jitter and accurate outputs, making it suitable for most pc, networking, and consumer applications. on the other hand, cy2037-3 contains a frequency select function in place of the power-down and output enable modes. for example, consumer products often require frequency compatibility with different electrical standards around the world. with this frequency select feat ure, a product that incorporates cy2037-3 could be compatible with both ntsc for north american, and pal for europe by simply changing the fs line. the twice programmable feature is absent in cy2037-3, because the second eprom row is now being used for the alternate frequency. table 1. device functiona lity: output frequencies parameter description condition min max unit fo output frequency v dd = 4.5 v to 5.5 v 1 133 mhz v dd = 3.0 v to 3.6 v 1 100 mhz v dd = 2.7 v to 3.0 v 1 66 mhz
cy2037 document number: 38-07354 rev. *k page 2 of 16 logic block diagram x g pd#/oe x d configuration crystal clkout / 1, 2, 4, 8, 16, 32, 64, 128 oscillator or fs mux high accuracy pll eprom
cy2037 document number: 38-07354 rev. *k page 3 of 16 contents die pad description . ............... ........... ........... ........... ......... 4 die pad summary ............................................................. 4 eprom configuration block ........................................... 5 pll output frequency ..................................................... 5 power management features .......................................... 5 crystal oscillator tuning circuit .................................... 5 cy2037 vs cy2037-2 ................ .............. .............. ............ 6 frequency select feature of cy2037-3 ......... ........... ...... 6 inkless die pick map (dpm) format ................................ 6 absolute maximum ratings ............................................ 7 operating conditions ....................................................... 7 electrical characteristics ................................................. 8 output clock switching characteristics ........................ 9 switching waveforms .................................................... 11 ordering information ...................................................... 13 ordering code definitions ..... .................................... 13 acronyms ........................................................................ 14 reference documents .................................................... 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc? solutions ...................................................... 16 cypress developer community ................................. 16 technical support ................. .................................... 16
cy2037 document number: 38-07354 rev. *k page 4 of 16 die pad description x y v dd v dd x d x g pd#/oe or fs n/c clkout v ss v ss horizontal scribe x x n/c device name vertical scribe 1 3 2 5 6 7 4 8 11 9 10 bond pad opening: 85 ? m x 85 ? m pad pitch: 125 ? m x 125 ? m (pad center to pad center) y (vertical) = 3.1 mils / 80 ? m x (horizontal) = 3.1mils / 80 ? m scribe: y = 40.9 mils / 1039.4 ? m x = 55.9 mils / 1420.1 ? m active die size: note: bottom side of die can be connected to vss or can be isolated. do not connect to v dd . CY2037EBWAF-IL 7c80383a cy2037-2waf-il 7c80381a cy2037-311waf-il 7c80340a cy2037-209waf-il 7c80381a die pad summary name die pad x coordinate ( ? m) y coordinate ( ? m) description v dd 1, 2 124.7 855.6, 731 voltage supply v ss 8, 9 1291.35 99.6, 225.2 ground x d 4 124.7 481.8 crystal connection x x 3 124.7 606.4 no connect [1] x g 6 124.7 232.6 crystal connection pd#/oe or fs 7 124.7 108 cy2037 and cy2037-2: epr om-programmable power-down or output enable pad cy2037-3: frequency select. serves as v pp in programming mode for all devices clkout 11 1282.45 901.8 clock output. also serves as three-state input during programming. n/c 5, 10 124.7, 1282.45 357.2, 769.4 no co nnect (so do not bond to these pads) note 1. for customers not bonding the x d or x g pad to external pins, an alternative bonding option would be shorting the xx pad to the x d pad.
cy2037 document number: 38-07354 rev. *k page 5 of 16 eprom configuration block ta b l e 2 summarizes the features that are configurable by eprom. refer ?7c8038x/7c8034x proprietary specification? for further details. this specif ication can be obtained from your cypress factory representative. . pll output frequency cy2037 contains a high resolution pll with 12-bit multiplier and 10-bit divider. the output frequency of the pll is determined by the following formula: in this formula, p is the feedback counter value and q is the reference counter value. p and q are eprom programmable values. power management features cy2037 contains eprom-programmable pd# and oe functions. if power-down (pd#) is selected, all active circuitry on the chip is shut down, output is tri-stated and pulled low by a weak pull-down when the control pin goes low. the weak pull-down is easily overdriven by another active clkout for applications that require mult iple clkouts on a single signal path.the oscillator and pll circuits must relock when the part leaves the power-down mode. if output enable (oe) mode is selected, the output is tri-stated and weakly pulled low when the control pin goes low. in this mode the oscillator and pll circuits continue to operate, allowing a rapid return to normal operation when the control input is deasserted. in addition, the pd# and oe modes can be programmed to occur synchronously or asynchronously with respect to the output signal. when the asynchronous setting is used, the power-down or output disable occurs immediately (allowing for logic delays), regardless of the position in the clock cycle. however, when the synchronous setting is used, the part waits for a falling edge at the output before the power-d own or output enable signal is initiated, thus preventing output glitches. in asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the nex t falling edge of the output. crystal oscillator tuning circuit cy2037 contains a unique tuning circuit to fine-tune the output frequency of the device. the tuning circuit consists of an arra y of eleven load capacitors on both sides of the oscilla tor drive inverter. the capacitor load values are eprom-programmable and may be increased in small increments. as the capacitor load is increas ed the circuit is fine-tuned to a lower frequency. the capacitor load values vary from 0.17 pf to 8 pf for a 100:1 tota l control ratio. the tuning increments are shown in table 3 on page 6 . refer to ?7c8038x/7c8034x proprietary specification? for further details. figure 1. crystal oscillator tuning circuit table 2. eprom adjustable features adjustable features adjust frequency feedback counter value (p) reference counter value (q) output divider selection oscillator tuning (load capacitance values) duty cycle levels (ttl or cmos) power management mode (oe or pd#) power management timing (synch ronous or asynchronous) f pll 2p5 + ?? ? q2 + ?? --------------------------- f ref ? = cd = eprom bit cd6 c6 cd5 c5 cd4 c4 cd3 c3 cd2 c2 cd1 c1 cd0 c0 cd3 c7 cd4 c8 cd5 c9 cd6 c10 external crystal cgo cdo rf c = load capacitor
cy2037 document number: 38-07354 rev. *k page 6 of 16 cy2037 vs cy2037-2 cy2037 contains a shadow register in addition to the eprom register. the shadow register is an exact copy of the eprom register and is the default register when the valid bit is not set. it is useful when the pr ototype or production environment calls for measuring and adjusting the clkout frequency several times. multiple adjustments can be pe rformed with the shadow register. after the required frequency is achieved the eprom register is permanently programmed. some production flows do not require the use of the shadow register. if this is the case, then cy2037-2 is the chosen device and cy2037-2 has a disabled shadow register. cy2037-3 contains the shadow register. frequency select feature of cy2037-3 cy2037-3 contains a frequency select function in place of the power-down and the output enable functions. with the frequency select feature, customers can switch two different frequencies that are configured in the two eprom rows. table 4 lists the definition of the frequency select pin (fs). inkless die pick map (dpm) format cypress ships inkless wafe rs to customers with an accompanying die pick map, which is used to determine the good die for assembly and programming. customers can also access individual dpm files at their convenience through ftp.cypress.com with a valid user account login and password. contact your local cypress field application engineer (fae) or sales representative for a cust omer ftp account. the dpm files are named with the fab lot number and wafer number scribed on the wafer. the dpm files are transferred to the customer?s ftp account when the factory ships out the wafers against their purchase order (po). table 3. crystal oscillator parameter parameter description min typ max unit r f feedback resistor, v dd = 4.5 v to 5.5 v feedback resistor, v dd = 2.7 v to 3.6 v 0.5 1.0 2 4 3.5 9.0 m ? m ? capacitors have 20% tolerance c g gate capacitor ? 13 ? pf c d drain capacitor ? 9 ? pf c 0 series capacitor ? 0.27 ? pf c 1 series capacitor ? 0.52 ? pf c 2 series capacitor ? 1.00 ? pf c 3 series capacitor ? 0.7 ? pf c 4 series capacitor ? 1.4 ? pf c 5 series capacitor ? 2.6 ? pf c 6 series capacitor ? 5.0 ? pf c 7 series capacitor ? 0.45 ? pf c 8 series capacitor ? 0.85 ? pf c 9 series capacitor ? 1.7 ? pf c 10 series capacitor ? 3.3 ? pf table 4. frequency select pin decoding for cy2037-3 fs pin output frequency 0 from eprom row 0 configuration 1 from eprom row 1 configuration
cy2037 document number: 38-07354 rev. *k page 7 of 16 absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. [2] supply voltage .......................... ...................?0.5 v to +7.0 v input voltage ....................................... ?0.5 v to v dd + 0.5 v storage temperature (non-condensing) ..... 55 c to +150 c junction temperature ............................... ?40 c to +100 c static discharge voltage (per mil-std-883, method 3015) .............. ............... 2000 v operating conditions parameter description min max unit v dd supply voltage (3.3 v) supply voltage (5.0 v) 2.7 4.5 3.6 5.5 v v t aj [3] operating temperature, junction ?10 +100 ? c c ttl max. capacitive load on outputs for ttl levels v dd = 4.5 v to 5.5 v, output frequency = 1 mhz to 40 mhz v dd = 4.5 v to 5.5 v, output frequency = 40 mhz to 133 mhz ? 50 25 pf pf c cmos max. capacitive load on outputs for cmos levels v dd = 4.5 v to 5.5 v, output frequency = 1 mhz to 66.6 mhz v dd = 4.5 v to 5.5 v, output frequency = 66.6 mhz to 133 mhz v dd = 3.0 v to 3.6 v, output frequency = 1 mhz to 40 mhz v dd = 3.0 v to 3.6 v, output frequency = 40 mhz to 100 mhz v dd = 2.7 v to 3.0 v, output frequency = 1 mhz to 66 mhz ? 50 25 30 15 15 pf pf pf pf pf x ref reference frequency, input crystal. fundamental tuned crystals only 10 30 mhz t pu power up time for all v dd ?s to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms notes 2. stresses greater than listed can impair the life of the device. 3. this product is sold in die form so operating conditi ons are specified for the die, or junction temperature.
cy2037 document number: 38-07354 rev. *k page 8 of 16 electrical characteristics over the operating range parameter [4] description test conditions min typ max unit v il low-level input voltage v dd = 4.5 v to 5.5 v v dd = 2.7 v to 3.6 v ??0.8 0.2 v dd v v v ih high-level input voltage v dd = 4.5 v to 5.5 v v dd = 2.7 v to 3.6 v 2.0 0.7 v dd ??v v v ol low-level output voltage v dd = 4.5 v to 5.5 v, i ol = 16 ma v dd = 2.7 v to 3.6 v, i ol = 8 ma ??0.4 0.4 v v v ohcmos high-level output voltage, cmos levels v dd = 4.5 v to 5.5 v, i oh = ?16 ma v dd = 2.7 v to 3.6 v, i oh = ?8 ma v dd ? 0.4 v dd ? 0.4 ??v v v ohttl high-level output voltage, ttl levels v dd = 4.5 v to 5.5 v, i oh = ?8 ma 2.4 ? ? v i il input low-current v in = 0 v ? ? 10 ? a i ih input high-current v in = v dd ??5 ? a i dd power supply current, unloaded v dd = 4.5 v to 5.5 v, output frequency ? 133 mhz v dd = 2.7 v to 3.6 v, output frequency ? 100 mhz ??45 25 ma ma i dds [5] standby current v dd = 2.7 v to 3.6 v ? 10 50 ? a r up input pull-up resistor v dd = 4.5 v to 5.5 v, v in = 0 v v dd = 4.5 v to 5.5 v, v in = 0.7 v dd 1.1 50 3.0 100 8.0 200 m ? k ? i pd_clkout clkout pull-down current (oe or pd# mode) v dd = 5.0 v ? 20 ? ? a notes 4. this part was characterized in a 20-pin soic package with external crystal, electr ical characteristics can change with other package types. 5. if external reference is used, it is required to st op the reference (set reference to low) during power-down.
cy2037 document number: 38-07354 rev. *k page 9 of 16 output clock switching characteristics over the operating range parameter [6] description test conditions min typ max unit t 1w output duty cycle at 1.4 v, v dd = 4.5 v to 5.5 v t 1w = t 1a ? t 1b figure 2 on page 11 . 1 mhz to 40 mhz, c l ?? 50 pf 40 mhz to 66 mhz, c l ? 15 pf 66 mhz to 125 mhz, c l ?? 25 pf 125 mhz to 133 mhz, c l ?? 15 pf 45 45 40 40 ? 55 55 60 60 % % % % t 1x output duty cycle at v dd /2, v dd = 4.5 v to 5.5 v t 1x = t 1a ? t 1b figure 2 on page 11 . 1 mhz to 66.6 mhz, c l ? 25 pf 66.6 mhz to 125 mhz, c l ? 25 pf 125 mhz to 133 mhz, c l ? 15 pf 45 40 40 ? 55 60 60 % % % t 1y output duty cycle at v dd /2, v dd = 3.0 v to 3.6 v t 1y = t 1a ? t 1b figure 2 on page 11 . 1 mhz to 40 mhz, c l ? 30 pf 40 mhz to 100 mhz, c l ?? 15 pf 45 40 ? 55 60 % % t 1z output duty cycle at v dd /2, v dd = 2.7 v to 3.0 v t 1z = t 1a ? t 1b figure 2 on page 11 . 1 mhz to 40 mhz, c l ? 15 pf 40 mhz to 66.6 mhz, c l ? 10 pf 40 40 ? 60 60 % % t 2 output clock rise time figure 3 on page 11 . between 0.8 v to 2.0 v, v dd = 4.5 v to 5.5 v, c l = 50 pf between 0.8 v to 2.0 v, v dd = 4.5 v to 5.5 v, c l = 25 pf between 0.8 v to 2.0 v, v dd = 4.5 v to 5.5 v, c l = 15 pf between 0.2 v dd to 0.8 v dd , v dd = 4.5 v to 5.5 v, c l = 50 pf between 0.2 v dd to 0.8 v dd , v dd = 3.0 v to 3.6 v, c l = 30 pf between 0.2 v dd to 0.8 v dd , v dd = 2.7 v to 3.6 v, l = 15 pf ? ? 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 3 output clock fall time figure 3 on page 11 . between 0.8 v to 2.0 v, v dd = 4.5 v to 5.5 v, c l = 50 pf between 0.8 v to 2.0 v, v dd = 4.5 v to 5.5 v, c l = 25 pf between 0.8 v to 2.0 v, v dd = 4.5 v to 5.5 v, c l = 15 pf between 0.2 v dd to 0.8 v dd , v dd = 4.5 v to 5.5 v, c l = 50 pf between 0.2 v dd to 0.8 v dd , v dd = 3.0 v to 3.6 v, c l = 30 pf between 0.2 v dd to 0.8 v dd , v dd = 2.7 v to 3.6 v, c l = 15 pf ? ? 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 4 startup time out of power-down figure 4 on page 11 . pd# pin low to high [7] ? 1 2 ms notes 6. not all parameters measured in production testing. 7. oscillator start time cannot be guaranteed for all crystal type s. this specification is for operation with at cut crystals wi th esr < 70 ohms.
cy2037 document number: 38-07354 rev. *k page 10 of 16 t 5a power-down delay time (synchronous setting) figure 4 on page 11 . pd# pin low to output low (t = period of output clk) ? t/2 t + 10 ns t 5b power-down delay time (asynchronous setting) figure 4 on page 11 . pd# pin low to output low ? 10 15 ns t 6 power-up time figure 5 on page 11 . from power-on [8] ? 1 2 ms t 7a output disable time (synchronous setting) figure on page 13 . oe pin low to output high z (t = period of output clk) ? t/2 t + 10 ns t 7b output disable time (asynchronous setting) figure on page 13 . oe pin low to output high z ? 10 15 ns t 8 output enable time (always synchronous enable) figure on page 13 . oe pin low to high (t = period of output clk) ? t 1.5t + 25 ns t 9 peak-to-peak period jitter figure 7 on page 12 . v dd = 4.5 v to 5.5 v, f o > 33 mhz, vco > 100 mhz v dd = 2.7 v to 3.6 v, f o > 33 mhz, vco > 100 mhz v dd = 2.7 v to 5.5 v, f o < 33 mhz ? 100 125 250 125 200 1% of f o ps ps ps output clock switching characteristics (continued) over the operating range parameter [6] description test conditions min typ max unit note 8. oscillator start time cannot be guaranteed for all crystal type s. this specification is for operation with at cut crystals wi th esr < 70 ohms.
cy2037 document number: 38-07354 rev. *k page 11 of 16 switching waveforms figure 2. duty cycle timing (t 1w, t 1x, t 1y , t 1z ) figure 3. output rise/fall time figure 4. power down timing (synchronous and asynchronous modes) figure 5. power-up timing t 1a t 1b output output t 2 v dd 0 v t 3 clkout v dd t 4 1/f t 5a v il v ih power down 0v 1/f t 5b clkout t (synchronous [ 9] ) (asynchronous [ 10] ) clkout v dd t 6 1/f v dd ? 10% power up 0 v min. 50 ? s max. 50 ms notes 9. in synchronous mode the power down or output tri-state is not initiated until the next falling edge of the output clock. 10. in asynchronous mode the power down or output tri-state occu rs within 25 ns regardless of position in the output clock cycle .
cy2037 document number: 38-07354 rev. *k page 12 of 16 figure 6. output enable timing (synchronous and asynchronous modes) figure 7. period jitter switching waveforms (continued) clkout v dd output enable 0 v v il v ih t 7a t 8 high impedance clkout t 7b t 8 high impedance t (synchronous [ 11] ) (asynchronous [ 12] ) clk 50% t9 notes 11. in synchronous mode the power down or output tri-state is not initiated until the next falling edge of the output clock. 12. in asynchronous mode the power down or output tri-state occu rs within 25 ns regardless of position in the output clock cycle .
cy2037 document number: 38-07354 rev. *k page 13 of 16 ordering information ordering code definitions ordering code type wafer thickness operating range CY2037EBWAF-IL inkless wafer 14 0.5 mils ?10 ? c to 100 ? c cy2037-2waf-il inkless wafer 14 0.5 mils ?10 ? c to 100 ? c cy2037-311waf-il inkless wafer 11 0.5 mils ?10 ? c to 100 ? c cy2037-209waf-il inkless wafer 8.66 0.3 mils ?10 ? c to 100 ? c fixed for inkless wafer wafer thickness: xx = 11 or 09 or blank ?11? for 11 mils; ?09? for 8.66 mils, blank for 14 mils part version: x = 2, 3 or blank for base part die revision: eb or none part identifier company id: cy = cypress waf-il xx x - xx 2037 cy
cy2037 document number: 38-07354 rev. *k page 14 of 16 acronyms reference documents reference documents are available through your local cypress sales representative. you can also direct your requests to tsbusdev@cypress.com . document conventions units of measure acronym description clkout clock output cmos complementary metal oxide semiconductor dpm die pick map eprom erasable programmable read only memory ntsc national televisi on system committee oe output enable pal phase alternate line pd power down pll phase locked loop ppm parts per million ttl transistor-transistor logic document number document title description 71-00005 7c8038x/7c8034x proprietary specification appendix c contains programming specification for customer use symbol unit of measure symbol unit of measure c degrees celsius w micro watts db decibels ma milli amperes dbc/hz decibels relative to the carrier per hertz mm milli meters fc femto coulomb ms milli seconds ff femto farads mv milli volts hz hertz na nano amperes kb 1024 bytes ns nano seconds kbit 1024 bits nv nano volts khz kilo hertz ? ohms k ? kilo ohms pa pico amperes mhz mega hertz pf pico farads m ? mega ohms pp peak-to-peak a micro amperes ppm parts per million f micro farads ps pico seconds h micro henrys sps samples per second s micro seconds ? sigma: one standard deviation v micro volts vrms micro volts root-mean-square
cy2037 document number: 38-07354 rev. *k page 15 of 16 document history page document title: cy2037, high accuracy eprom programmable pll die for crystal oscillators document number: 38-07354 revision ecn orig. of change submission date description of change ** 112248 dsg 03/01/02 change from spec number: 38-00679 to 38-07354 *a 121857 rbi 12/14/02 power up requirements added to operating conditions information *b 291092 rgl see ecn updated min. operating temperature, junction *c 522769 rgl see ecn added cy2037b information. updated absolute maximum junction temperature specification. updated ordering information table. added die pad description and coordinates *d 804376 rgl see ecn minor change: to post on web *e 2192266 dpf / pyrs see ecn added inkless die information. *f 2748211 tsai 08/10/09 posting to external web. *g 2761988 kvm 09/14/09 add CY2037EBWAF-IL to ordering information table remove obsolete part numbers: cy2037awaf, cy2037-2waf, cy2037-3waf, cy2037-3waf-il. removed status column in ordering in formation table; replaced with footnotes *h 2906472 cxq 04/07/2010 removed inactive part from ordering information table. *i 3022612 bash 09/03/2010 post divider number corrected in ?feature? section from 16 to 8 on page 1. removed all references of obsolete parts(cy2037a) and benefits section from page 1.(cti die scribe: x(horizontal)= 2.6 mils/65.6 m, y(vertical)=3.0 mils/76.9 m) die diagram on page 3 updated with pad numbers, scribe dimensions for tsmc part, device name table, note for bottom side of die connection. ?t? for transistor removed from figure 1 on page 4 as it is not mentioned in figure anywhere. changed parameter name to i pd_clockout and clarified its description in electrical characteristics table on page 7. added figure 6 and 7 for oe and period jitter on page 9. part numbers cy2037eb and cy2037-311 added in ordering information on page 9. added ordering code definitions. added acronyms, reference documents and document conventions. *j 3069175 bash 10/25/2010 removing cy2037b from die pad description on page 4, ordering information and ordering code definitions. *k 4175824 cinm 11/13/2013 updated die pad description . updated ordering information (added new part number cy2037-209waf-il). updated in new template. completing sunset review.
document number: 38-07354 rev. *k revised november 13, 2013 page 16 of 16 purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy2037 ? cypress semiconductor corporation, 2010-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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